How to do lvs for mixed signal circuit with Assura or Calibre

[ykjing]

Hi, could someone kindly help me with the lvs for a mixed digital and analog
circuit by Assura or Calibre. I can do lvs for them alone successfuly, but
can not do lvs when they are connected together in Cadence. Is there any
guide or website should I refer to?

Many thanks in advance!

Regards.
Fred

[Riad KACED]

Dear Fred,

Yes of course, AMS designs are supported for LVS.
What does it mean " ... but can not do lvs when they are connected
together in Cadence" ?
What is the issue ? Any error messages ? Device/Connectivity/Property
mismatch ? Or mixed up with the substrates ?

Any detailed description of your problems is more than welcome ;-)

Riad.

[ykjing]

Dear Riad,
Thank you for your quick reply.
I have generated a digital circuit, PostDiv, by Astro and LVSed it by
Calibre, using V2LVS to generate a source netlist.
Then the digital circuit's gds and .v file was imported into Cadence. It has
layout view/schematic view/symbol. The digital circuit PostDiv's symbol was
put into an existing analog cell DMP's schematic, then wired them together.
The PostDiv's layout was put into the DMP layout. After issuing the Calibre
lvs command, the status window said:
waiting for layout viewer to export cell ...
waiting for schematic viewer to export cell..
schematic export filed or was cancelled. please consult the transcript in
the source window.Then it stopped.

The CIW window had the following info:
...
Running Artist Hierarchical Netlisting ...
ERROR: Netlister: unable to descend into any of the views defined in the
view list: "auCdl schematic cmos_sch" for instance U5 in cell PostDiv.
Either add one of these views to: Library: PostDiv1 Cell: MX2X1 or modify
the view list to contain an existing view.
End netlisting May 12 22:02:07 2008
ERROR (OSSHNL): Error(s) found during netlisting. The netlist may be corrupt
or may not be produced at all.
To generate correct netlist, fix the errors and re-netlist.
mv: cannot access /export/home/chenym/jingyk/gps/1/cds/lvs/si.sav
...

I have added " LVS BOX PostDiv" to LVS rule file to ignore the digital part,
but it can not help. The above error still exist.
How I can pass the top level LVS?

Thank you in advance.
Fred.

Post by Riad KACED
Dear Fred,
Yes of course, AMS designs are supported for LVS.
What does it mean " ... but can not do lvs when they are connected
together in Cadence" ?
What is the issue ? Any error messages ? Device/Connectivity/Property
mismatch ? Or mixed up with the substrates ?
Any detailed description of your problems is more than welcome ;-)
Riad.

[ykjing]

Hi,
I have solved the problem by adding standard digital gates'schematic view to
its view list.
I can run the calibre LVS now.

Thank you all.
Regards.
Fred.

Post by ykjing
Dear Riad,
Thank you for your quick reply.
I have generated a digital circuit, PostDiv, by Astro and LVSed it by
Calibre, using V2LVS to generate a source netlist.
Then the digital circuit's gds and .v file was imported into Cadence. It
has layout view/schematic view/symbol. The digital circuit PostDiv's
symbol was put into an existing analog cell DMP's schematic, then wired
them together. The PostDiv's layout was put into the DMP layout. After
waiting for layout viewer to export cell ...
waiting for schematic viewer to export cell..
schematic export filed or was cancelled. please consult the transcript in
the source window.Then it stopped.
...
Running Artist Hierarchical Netlisting ...
ERROR: Netlister: unable to descend into any of the views defined in the
view list: "auCdl schematic cmos_sch" for instance U5 in cell PostDiv.
Either add one of these views to: Library: PostDiv1 Cell: MX2X1 or modify
the view list to contain an existing view.
End netlisting May 12 22:02:07 2008
ERROR (OSSHNL): Error(s) found during netlisting. The netlist may be
corrupt or may not be produced at all.
To generate correct netlist, fix the errors and re-netlist.
mv: cannot access /export/home/chenym/jingyk/gps/1/cds/lvs/si.sav
...
I have added " LVS BOX PostDiv" to LVS rule file to ignore the digital
part, but it can not help. The above error still exist.
How I can pass the top level LVS?
Thank you in advance.
Fred.

Post by Riad KACED
Dear Fred,
Yes of course, AMS designs are supported for LVS.
What does it mean " ... but can not do lvs when they are connected
together in Cadence" ?
What is the issue ? Any error messages ? Device/Connectivity/Property
mismatch ? Or mixed up with the substrates ?
Any detailed description of your problems is more than welcome ;-)
Riad.

[Riad KACED]

Hi Fred,

Sorry for leaving you alone, I was absent from the forum for the past
couple of days.
But this had a positive effect since you've managed to work it out
yourself, well done !
I would have proposed adding the 'functional' view to your stop list
when netlisting and include the DIGITAL.cdl netlist when your run your
LVS extract/compare with calibre. I guess your digital verilog import
to Cadence comes with a 'functional'' view

Anyway, y've made it working and that's the most important !

Riad.

[ykjing]

Thanks Riad. I really appreciate your help. :)

Post by Riad KACED
Hi Fred,
Sorry for leaving you alone, I was absent from the forum for the past
couple of days.
But this had a positive effect since you've managed to work it out
yourself, well done !
I would have proposed adding the 'functional' view to your stop list
when netlisting and include the DIGITAL.cdl netlist when your run your
LVS extract/compare with calibre. I guess your digital verilog import
to Cadence comes with a 'functional'' view
Anyway, y've made it working and that's the most important !
Riad.